Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n
For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n
Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n The useful workflow is to join three timelines: process crash timestamps, kernel log entries and EDAC counters. Export all three to the same monitoring system and overlay them for a 90 day window. A crash that sits within 10 minutes of a correctable event on the same node is strong evidence that memory is the root cause, even though the corrected bit was not the crash itself \u2014 it points at a degrading DIMM.<\/p>\n\n\n\n For crashes with no memory events nearby, enable kernel core dumps and inspect the faulting address against the node’s physical memory map. A fault in a page allocated to a long-lived arena, is the second clue. Both together justify a DIMM swap.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n The useful workflow is to join three timelines: process crash timestamps, kernel log entries and EDAC counters. Export all three to the same monitoring system and overlay them for a 90 day window. A crash that sits within 10 minutes of a correctable event on the same node is strong evidence that memory is the root cause, even though the corrected bit was not the crash itself \u2014 it points at a degrading DIMM.<\/p>\n\n\n\n For crashes with no memory events nearby, enable kernel core dumps and inspect the faulting address against the node’s physical memory map. A fault in a page allocated to a long-lived arena, is the second clue. Both together justify a DIMM swap.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n The useful workflow is to join three timelines: process crash timestamps, kernel log entries and EDAC counters. Export all three to the same monitoring system and overlay them for a 90 day window. A crash that sits within 10 minutes of a correctable event on the same node is strong evidence that memory is the root cause, even though the corrected bit was not the crash itself \u2014 it points at a degrading DIMM.<\/p>\n\n\n\n For crashes with no memory events nearby, enable kernel core dumps and inspect the faulting address against the node’s physical memory map. A fault in a page allocated to a long-lived arena, is the second clue. Both together justify a DIMM swap.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n The useful workflow is to join three timelines: process crash timestamps, kernel log entries and EDAC counters. Export all three to the same monitoring system and overlay them for a 90 day window. A crash that sits within 10 minutes of a correctable event on the same node is strong evidence that memory is the root cause, even though the corrected bit was not the crash itself \u2014 it points at a degrading DIMM.<\/p>\n\n\n\n For crashes with no memory events nearby, enable kernel core dumps and inspect the faulting address against the node’s physical memory map. A fault in a page allocated to a long-lived arena, is the second clue. Both together justify a DIMM swap.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n The useful workflow is to join three timelines: process crash timestamps, kernel log entries and EDAC counters. Export all three to the same monitoring system and overlay them for a 90 day window. A crash that sits within 10 minutes of a correctable event on the same node is strong evidence that memory is the root cause, even though the corrected bit was not the crash itself \u2014 it points at a degrading DIMM.<\/p>\n\n\n\n For crashes with no memory events nearby, enable kernel core dumps and inspect the faulting address against the node’s physical memory map. A fault in a page allocated to a long-lived arena, is the second clue. Both together justify a DIMM swap.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n The useful workflow is to join three timelines: process crash timestamps, kernel log entries and EDAC counters. Export all three to the same monitoring system and overlay them for a 90 day window. A crash that sits within 10 minutes of a correctable event on the same node is strong evidence that memory is the root cause, even though the corrected bit was not the crash itself \u2014 it points at a degrading DIMM.<\/p>\n\n\n\n For crashes with no memory events nearby, enable kernel core dumps and inspect the faulting address against the node’s physical memory map. A fault in a page allocated to a long-lived arena, is the second clue. Both together justify a DIMM swap.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n\n\n The useful workflow is to join three timelines: process crash timestamps, kernel log entries and EDAC counters. Export all three to the same monitoring system and overlay them for a 90 day window. A crash that sits within 10 minutes of a correctable event on the same node is strong evidence that memory is the root cause, even though the corrected bit was not the crash itself \u2014 it points at a degrading DIMM.<\/p>\n\n\n\n For crashes with no memory events nearby, enable kernel core dumps and inspect the faulting address against the node’s physical memory map. A fault in a page allocated to a long-lived arena, is the second clue. Both together justify a DIMM swap.<\/p>\n\n\n\n Patrol scrubbing walks all of memory periodically and rewrites correctable errors before they become double-bit failures. Enable it and set the scrub rate to complete a full pass weekly. On the logging side, make sure Also make the counters survivable across reboots. EDAC counters reset at boot on most platforms, so persist the cumulative total into your metrics backend rather than trusting Non-ECC has a real place. Stateless CI runners, short-lived build containers, load generators and caches that can be rebuilt from a source of truth tolerate bit flips because a corrupt result is either detected downstream or discarded. The math changes the moment the workload holds uncommitted state that no other system can reconstruct.<\/p>\n\n\n\n For game servers the deciding question is simple: if a value in memory is wrong, does the player lose progress? A world save, an economy ledger, a player inventory and an instance state all answer yes. That puts them in the ECC camp regardless of node size. A single redis-role cache or a metrics scraper does not.<\/p>\n\n\n\n Buying ECC memory is not the same as running with ECC active. On some consumer boards the modules run in non-ECC mode silently, and on some server platforms a mixed population disables correction. Confirm with Check that the EDAC driver loaded at boot and that each controller reports a CSR row count. If ECC does not reduce crash rate to zero, but it converts an entire class of unexplained failure into a logged, attributable event. That means a machine can be drained on evidence rather than superstition, and a warranty claim can cite the exact DIMM and the exact error count. Providers that ship ECC by default make this a non-issue; servers built on server-grade boards<\/a> generally do, while budget desktop hardware generally does not.<\/p>\n\n\n\n Before you spend another week chasing a physics exception, read the EDAC counters. They answer in ten seconds a question that log archaeology takes days to approach, and on a node that is supposed to stay up for months at a time, that answer is the difference between a stable service and a recurring incident.<\/p>\n\n A game server that has been running for six weeks crashes in the physics tick with a stack trace pointing at a heap pointer, restarts, and runs fine for another three weeks. The RAM passed twelve hours of memtest at installation. Nothing in the application logs explains it, and the same build runs without incident on a test machine that also uses cheap memory.<\/p>\n\n\n\n That pattern is the signature of silent bit errors in DRAM: a flip that occurs in a rarely touched page, goes uncorrected, and only surfaces when the corrupted value happens to be used as a pointer, an index or a checksum. ECC memory does not stop the flip. It stops the flip from becoming an unexplained crash.<\/p>\n\n\n\n Non-ECC DRAM has no parity at all, so a single flipped bit is invisible to the platform. Cosmic ray and alpha particle events are rare per cell but not rare per server: the widely cited Google and Facebook fleets studies put correctable error rates at roughly one per several GB per hour under heavy load, which for a 64 GB node means multiple events a day. Server-class hardware<\/a> reports and corrects these silently.<\/p>\n\n\n\n Most of those flips land in a page that is rewritten before it is read, so nothing happens. The dangerous subset lands in a structure that lives for hours: a hash table, a connection object, an economy ledger cache. A single flipped bit in a pointer offset moves a read by 4 to 64 bytes and produces a detectable fault. A flipped bit in a length field produces a buffer overrun that the allocator may not catch for hours.<\/p>\n\n\n\n A desktop reboots daily, throws away its working set and reloads it from disk. A game node runs the same process image for weeks and keeps world state in memory across the entire period. Every byte of resident memory is exposed to the error rate continuously, and the longer the process lives, the more opportunity for a corrupt value to reach a code path where it matters.<\/p>\n\n\n\n Tick-based servers add a second amplifier: they read and write the same simulation state at a fixed rate, so a corrupted value in a frequently accessed structure is exercised thousands of times per minute instead of being abandoned. This is why crash reports cluster in the simulation loop rather than in request handling.<\/p>\n\n\n\n On ECC hardware the memory controller reports correctable and uncorrectable events through Machine Check Architecture. The kernel exposes them via the EDAC subsystem, and userspace reads them from Track the correctable error count as a time series. A flat zero is normal. A single correctable event in a month is normal. More than one per hour on a rank that has been healthy for a year is a warning sign, and an uncorrectable error rate above one per week means the machine should be drained now rather than after the next maintenance window.<\/p>\n\n\n\ndmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Correlating crashes with memory events<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Correlating crashes with memory events<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
When non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Correlating crashes with memory events<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Correlating crashes with memory events<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Correlating crashes with memory events<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
When non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Correlating crashes with memory events<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
When non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
Correlating crashes with memory events<\/h2>\n\n
Turning on scrub and logging properly<\/h2>\n\n
mcelog<\/code> or rasdaemon<\/code> is running under systemd and that its output reaches your central log store; a local-only log disappears with the disk.<\/p>\n\n\n\nce_count<\/code> after a power cycle.<\/p>\n\n\n\nWhen non-ECC is genuinely acceptable<\/h2>\n\n
Verifying the ECC path end to end<\/h2>\n\n
dmidecode -t memory<\/code> and look for Error Correction Type: Multi-bit ECC<\/code> and a non-zero total width.<\/p>\n\n\n\nedac-util -v<\/code> prints nothing, the platform is not exposing error reporting and you are running blind even if the memory is ECC. Boot firmware settings sometimes hide memory health reporting behind an option that defaults to off on older boards.<\/p>\n\n\n\nThe operational payoff<\/h2>\n\n
How silent corruption accumulates<\/h2>\n\n\n\n
Why long-running servers feel it more than desktops<\/h2>\n\n\n\n
Detection: mcelog, edac-util and the event log<\/h2>\n\n\n\n
\/sys\/devices\/system\/edac\/mc\/<\/code> or through mcelog<\/code>. Without this instrumentation ECC is inert: the hardware corrects the bit and nothing records the degradation.<\/p>\n\n\n\n# counters per memory controller \/ rank\ngrep -r . \/sys\/devices\/system\/edac\/mc\/*\/ce_count\nedac-util -v\n# decoded machine check events\nmcelog --client\njournalctl -k | grep -i \"machine check\\|corrected\"<\/code><\/pre>\n\n\n\n